Scaling of semiconductor devices (e.g., a metal-oxide semiconductor field-effect transistor) has enabled continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades. Continued scaling of MOSFETs results in severe degradation of carrier mobility, however, which in turn adversely affects the device drive current. To further enhance the performance of MOS devices, carrier mobility enhancement becomes a key element in developing next-generation technologies. Among efforts to improve carrier mobility, introducing stress into the channel region of MOS devices is widely adopted. Generally, it is desirable to induce a tensile stress in the channel region of an n-type metal-oxide-semiconductor (“NMOS”) device in a source-to-drain direction, and to induce a compressive stress in the channel region of a p-type metal-oxide-semiconductor (“PMOS”) device in a source-to-drain direction.
A commonly used method for applying compressive stress to the channel regions of PMOS devices is growing SiGe stressors in the source and drain regions of the respective PMOS devices. Such a method typically includes the steps of forming recesses in a silicon substrate along edges of gate spacers, epitaxially growing SiGe stressors in the recesses, and annealing. Since SiGe has a greater lattice constant than the silicon substrate does, after annealing, it applies a compressive stress to a channel region, which is located between a source SiGe stressor and a drain SiGe stressor.
The above-discussed method, however, suffers drawbacks when used for the formation of static random access memory (SRAM) cells. FIG. 1 illustrates an exemplary circuit diagram of a six-transistor SRAM cell, which includes pass-gate transistors PG1 and PG2, pull-up MOS devices PU1 and PU2 and pull-down MOS devices PD1 and PD2. Gates 2 and 4 of the respective pass-gate MOS devices PG1 and PG2 are controlled by word-lines WL that determines the selection of the current SRAM cell. A latch formed of pull-up MOS devices PU1 and PU2 and pull-down MOS devices PD1 and PD2 stores a state. The stored state can be read or written through a bit line BL.
Conventionally, on a memory chip, PMOS devices in both peripheral circuits and memory circuits are formed with SiGe stressors, which result in a significant improvement in the drive currents of the pull-up PMOS devices in SRAM cells. The drive currents of pull-down NMOS devices, however, are relatively difficult to improve, and thus have smaller drive currents. The unbalanced performance of PMOS and NMOS devices causes a writing problem. For example, the pull-up MOS device PU2 has a high drive current, hence a high ability for supplying charges from Vcc to node 6. Conversely, NMOS device PD2 has a relatively low drive current, hence a low ability for discharging charges from node 6 to Vss. Consequently, when a “0” is written into the memory cell, it takes a long period of time to write the state “0.” Additionally, write margins of the SRAM cells are degraded due to the high drive currents of PMOS devices. A low write margin results in an increased possibility of erroneous writing. To achieve high performance SRAM cells, read and write operations are preferably balanced. Therefore, it is preferred that the drive currents of pull-up PMOS devices and pull-down NMOS devices are balanced.
Conventionally, the drive currents of NMOS devices may be improved by increasing gate width of the NMOS devices. Such a solution, however, contradicts to the requirement of scaling integrated circuits. Particularly, memory devices need to have high densities. Therefore, increasing gate width of NMOS devices in memories is not a preferred method. A novel method for solving the above-discussed problem without causing the reduction in memory device densities is thus needed.